will be asserted during the SECOND clock cycle
after DAV 
is asserted.
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Postscript Version
Fall 1997 Dr. Havlicek
Revise your solution to HW3 so that only TWO comparators are used. The input
and output signals of this design are the same as those for HW3, except
that the MEDIAN output will be ready and
DAV will be asserted during the SECOND clock cycle
after DAV is asserted.
Use these devices:
NOTE: This design DOES require a control unit. Design the control unit using D flip-flops and combinational logic as needed.
